The present invention is generally directed to integrated circuits and, in particular, to a system for generating a reference voltage.
In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits, such as application-specific integrated circuit (ASIC) chips, random access memory (RAM) chips, microprocessor (uP) chips, and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices. A SOC device integrates into a single chip all (or nearly all) of the components of a complex electronic system, such as a wireless receiver (e.g., a cell phone, a television receiver, or the like). SOC devices greatly reduce the size, cost, and power consumption of the overall system.
Reductions in power consumption are particularly important in SOC devices. SOC devices are frequently used in portable devices that operate on battery power. Since maximizing battery life is a critical design objective in a portable device, it is essential to minimize the power consumption of SOC devices that may be used in the portable device. Furthermore, even if an SOC device is not used in a portable device, minimizing power consumption is still an important objective. The increased use of a wide variety of electronic products by consumers and businesses has caused corresponding increases in the electrical utility bills of homeowners and business operators. The increased use of electronic products also is a major contributor to the increased electrical demand that has caused highly publicized power shortages in the United States, particularly California.
To minimize power consumption in electronic devices, particularly SOC devices, many manufacturers have reduced the voltage levels at which electronic components operate. Low power integrated circuit (IC) technology operating at +3.3 volts replaced IC technology operating at +5.0 volts. The +3.3 volt IC technology was, in turn, replaced by +1.6 volt IC technology in many applications, particularly microprocessor and memory applications.
In deep sub-micron VLSI designs, two voltage sources for a chip design are common. One voltage source is an internal core power supply voltage that has a lower swing voltage than the second voltage source, which provides the output pad ring voltage. Common range values may include an internal source range of 1.0-1.5 volts and an external source range of 2.3-3.6 volts.
In order to use the lower core voltages effectively, the threshold voltages for the transistors are reduced. For example, the gate oxides may be thinned and the drain-to-source distances may be decreased to reduce threshold voltages for CMOS transistors. Reducing the threshold voltages in this way results in a decrease in the breakdown voltages of the lower threshold devices. Therefore, these thin-gate transistors operating at voltages of about 1.0 volt or lower have low voltage tolerances.
The internal core circuitry running on the internal source typically uses thin gate oxides and, thus, cannot tolerate the higher external voltages of 2.3-3.6 volts. The transistors used in the pad rings, which interface off the chip to the board and surrounding chips, use a thicker gate oxide and larger minimum L than internal transistors and hence can handle the larger external voltages. In order for the low voltage transistors to communicate across the boundary from the lower internal source to the higher external source, voltage level translation is used.
When chip technologies used internal voltages greater than 2 volts and external voltages were 3.3-5.5 volts, this level translation was relatively simple, and several different methodologies could be used. However, once internal voltages decreased to the 1 volt range, several of the previously used level translation methodologies could no longer be used.
In accordance with the present invention, a system for generating a reference voltage is provided that substantially eliminates or reduces disadvantages and problems associated with conventional systems and methods. In particular, different amounts of resistance are used to maintain the reference voltage at approximately the same voltage level regardless of the external power supply voltage level, and a charge assist circuit is included to more quickly charge the reference voltage.
According to one embodiment of the present invention, a system for generating a reference voltage is provided that includes a first p-type, thick-gate transistor, a second p-type, thick-gate transistor, a third p-type, thick-gate transistor, and a fourth p-type, thick-gate transistor. The first p-type transistor has a source that is coupled to an external power supply, a gate, and a drain that is coupled to the gate. The second p-type transistor has a source that is coupled to the drain of the first p-type transistor, a gate, and a drain that is coupled to the gate. The third p-type transistor has a source that is coupled to the drain of the second p-type transistor, a gate that is operable to receive a mode indicator, and a drain that is coupled to ground. The fourth p-type transistor has a source that is coupled to the drain of the second p-type transistor, a gate that is operable to receive an inverted mode indicator, and a drain that is coupled to ground.
Technical advantages of one or more embodiments of the present invention include providing an improved system for generating a reference voltage for a voltage level shifter. In a particular embodiment, different amounts of resistance are provided between the reference voltage and ground depending on the mode in which the voltage level shifter is operating. As a result, the difference in voltage levels between an external power supply and the reference voltage is less when the external power supply is lower than when the external power supply is greater. Accordingly, the reference voltage may be maintained at approximately the same voltage level regardless of the mode.
Technical advantages of one or more embodiments of the present invention also include providing a charge assist circuit. In a particular embodiment, the charge assist circuit includes a specified transistor that is shorter than a specified transistor in the reference voltage generator. As a result, more current initially flows through the transistor in the charge assist circuit than through the transistor in the reference voltage generator, resulting in the reference voltage being charged more quickly. In addition, the reference voltage eventually reaches a level at which the charge assist circuit is de-biased, such that the charge assist circuit is essentially placed in a standby mode after the reference voltage is charged. Accordingly, the DC current drawn by the charge assist circuit is minimized when its charging assistance is no longer being used.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.